1. Field of the Invention
The present invention relates to a data transmission circuit and a data transmission method. More specifically, the present invention relates to a data transmission circuit and a data transmission method in which data is input and output in a plurality of transmission modes.
2. Related Background Art
Conventionally, a computer and a peripheral device have been connected using an interface for peripheral devices such as a serial interface and a parallel interface. Recently, a universal serial bus (USB), IEEE1394 and other serial interfaces to connect a variety of peripheral devices have come into wide use to integrate and standardize interfaces.
Out of the need of the recent information society for high-speed communication of large volumes of data, USB 2.0 standard offering a faster data transfer rate than the conventional USB 1.x standard such as USB 1.0 standard (the standard of USB Implements Forum or USB-IF) has been developed. The USB 1.x standard has two connection modes: a full-speed mode transferring data at speeds up to 12 Mbps and a low-speed mode up to 1.5 Mbps. In addition to those two modes, the USB 2.0 standard further has a high speed mode supporting data rates of up to 480 Mbps, allowing high-speed communication of larger volumes of data.
In high-speed data transmission such as the USB standard, the waveform could be distorted due to the transmission line reflection effect. Therefore, highly accurate control of output impedance is required for an output buffer to keep the output impedance the same as the transmission line impedance.
For output impedance control, “A 660 MB/s Interface Megacell Portable Circuit in 0.3 μm-0.7 μm CMOS ASIC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 12, DECEMBER 1996, for example, describes a method of switching the transistor size to control an output buffer drive capacitance. According to the method, control of the output buffer drive capacitance adjusts output impedance with respect to fluctuations of production, power supply voltage, and temperature to optimize the output impedance.
Further, in high-speed data transmission, it is also important to control a slew rate by an output buffer to prevent the rapid voltage change from generating noise to other units. Therefore, the waveform is controlled to change with slow rising and falling edges.
A proposed method for controlling a slew rate using an output buffer, for example, is to provide a feedback capacitor between an output terminal of the output buffer and a signal line driving final stage transistors, which is described in “DESIGN GUIDE FOR A LOW SPEED BUFFER FOR THE UNIVERSAL SERIAL BUS”, Revision1.1 December, 1996 Intel Corporation. According to the method, the feedback capacitor optimizes the rising and falling of a waveform while preventing a rapid change of output signals for suitable data transmission.
The above conventional methods applied to an output buffer of a CMOS push/pull constant voltage driver will be explained hereinbelow with reference to FIGS. 3 and 4 as a conventional output buffer circuit.
As shown in FIG. 3, a conventional output buffer has a main buffer 101 outputting a high logic level (which will be abbreviated hereinafter as a H-main buffer 101), a main buffer 102 outputting a low logic level (as a L-main buffer 102), impedance control terminals 103a, 103b, 103c, and 103d selecting drive transistors, a low level transmission circuit 104 (as a L-transmission circuit 104), and a high level transmission circuit 105 (as a H-transmission circuit 105). The output buffer further has a prebuffer 106 driving the main buffers, a feedback capacitor 108 connected between an output PAD 107 and the prebuffer 106, and a data input terminal 109.
The L-main buffer 102 includes a plurality of Nch transistors 111a, 111b, 111c, and 111d connected between the output PAD 107 and a ground line 110.
The size of each of the Nch transistors 111a to 111d is determined considering a control range, control width and the like to attain optimal output impedance by the combination of control signals input to the impedance control terminals 103a to 103d. For example, different impedance value is assigned to each of the Nch transistors 111a to 111d by weighing for optimal output impedance.
The L-transmission circuit 104 has transistor selection circuits 121, each of which connected to each of the impedance control terminals as well as with each of the Nch transistors of the L-main buffer 102. In this configuration, when an impedance control signal is input to the impedance control terminal 103a, for example, a gate electrode of the Nch transistor 111a of the L-main buffer 102 is clamped to the ground line 110.
A transmission gate 112a of the L-transmission circuit 104 is controlled by an impedance control signal input to the impedance control terminal 103a. Via the transmission gate 112a, the prebuffer 106 is connected to the Nch transistor 111a of the L-main buffer 102.
A clamp Nch transistor 114a is controlled by the impedance control signal from an inverter 113a. The inverter 113a inverts and outputs the control signal. By the Nch transistor 114a, the gate electrode of the Nch transistor 111a of the L-main buffer 102 is clamped to the ground line 110.
The H-main buffer 101 has substantially the same configuration as the L-main buffer, in which the Nch transistor 111a to 111d are replaced with a plurality of Pch transistors (not shown) connected between the output PAD 107 and a power line 115.
The H-transmission circuit 105 has substantially the same configuration as the L-transmission circuit 104, having transistor selecting circuits, each of which connected to each of the impedance control terminals as well as with each of the Pch transistors of the H-main buffer 101. When an impedance control signal is input to the impedance control terminal, a gate electrode of the Pch transistor of the H-main buffer 101 is clamped to the power line 115.
The prebuffer 106 is an inverter. The prebuffer 106 inverts a data signal input through the data input terminal 109, and then outputs the inverted signal to the transmission gate of the L-transmission circuit 104 or H-transmission circuit 105. The feedback capacitor 108 is provided between the prebuffer 106 and the output PAD 107 to prevent a sharp edge of an output signal from the output PAD 107.
Operations of the conventional output buffer having the above configuration will be explained hereinbelow with reference to FIGS. 3 and 4. In data transmission, a control code optimized to obtain a desired value of data output impedance is input as impedance control signals to the impedance control terminals 103a to 103d. The impedance control signal, being a logic high or low, is input to the impedance control terminal as a digital high or low voltage.
If an impedance control signal input to the impedance control terminal 103a is a high logic level, the L-transmission circuit 104 opens the transmission gate 112a. An output voltage of the prebuffer 106 is thereby released to send a data signal inverted by the prebuffer 106 to the Nch transistor 111a of the L-main buffer 102, selecting the transistor 111a as a drive transistor.
If the impedance control signal input to the impedance control terminal 103a is a low logic level, on the other hand, the L-transmission circuit 104 closes the transmission gate 112a. The output voltage of the prebuffer 106 is thereby blocked. At the same time, the clamp Nch transistor 114a of the L-transmission circuit 104 is turned on to fix the gate electrode of the Nch transistor 111a of the L-main buffer 102 to a ground potential. The Nch transistor 111a is thereby turned off not to be selected as a drive transistor.
The H-transmission circuit 105 operates in the same manner as the L-transmission circuit 104. If an impedance control signal input to the impedance control terminal 103a is a logic low, the H-transmission circuit 105 selects the Pch transistor of the H-main buffer 101 as a drive transistor. If the impedance control signal is a logic high, on the other hand, the H-transmission circuit 105 does not select the Pch transistor.
As described above, if a signal input to the data input terminal 109 is a logic low, the inverter 106 outputs a high level to output a ground level to the output PAD 107. If a signal input to the data input terminal 109 is a logic high, on the other hand, the inverter 106 outputs a low level to output a power supply voltage to the output PAD 107. With control of the level of the output PAD 107 in accordance with the level of the data input terminal 109, output impedance is adjusted for optimization with respect to fluctuations of production, power supply voltage, and temperature.
Further, when the output PAD 107 outputs data, the feedback capacitor 108 provided between the output PAD 107 and the prebuffer 106 controls the slew rate of an output waveform to optimize the rising and falling of the waveform.
However, the above output buffer has the followings problems. The output buffer controls output impedance by selecting the transistor (Pch transistor or Nch transistor) of the H-main buffer 101 or the L-main buffer 102 and changing the total size of the transistors. Switching of the drive transistors results in a change in the total size of the drive transistors and a change in the capacitance of the gate electrodes of the transistors.
Also, in the above output buffer, the slew rate of the output waveform is controlled by the load capacitance of the prebuffer 106, which is, the pre-optimized capacitance of the feedback capacitor 108 plus the capacitance of the gate electrodes of selected transistors of the H-main buffer 101 or L-main buffer 102.
Therefore, despite that the slew rate of an output waveform is to be optimized by the feedback capacitor 108, once the load capacitance of the prebuffer 106 is changed for output impedance control, it disables optimization of the slew rate of the output waveform.
On the other hand, optimizing the slew rate of the output waveform disables output impedance control. It is therefore impossible to control both output impedance and a slew rate.
For example, if a drive current to the transistors increases due to a temporal variation in operating temperature or a change in physical property of the transistor, the output impedance of the output buffer decreases. In this case, it is possible to change the impedance control code controlling the output impedance from CODE-A to CODE-B as shown in FIG. 4, for example, to compensate the decrease of the output impedance. The decrease of the output impedance is compensated by reducing a number of drive transistors of the H-main buffer 101 or L-main buffer 102. However, reduction of a number of transistors reduces the load capacitance of the prebuffer 106. The feedback capacitance thereby becomes insufficient, resulting in a sharp edge of an output waveform from the output PAD 107 after changing the impedance control codes.
Further, in output impedance control for production fluctuations of a semiconductor, a property variation of the transistor and that of the capacitor with respect to the production fluctuations do not always correspond to each other. Therefore, adjustment of a control code to fix output impedance with respect to production fluctuations causes the load capacitance of the prebuffer output to differ from a control code to a control code. There is thus a problem that the slew rate of an output waveform differs between control codes.
A method for solving the problem of changing slew rates resulted from impedance control is to employ a capacitor array composed of a plurality of unit capacitors. However, if an output slew rate is controlled by the capacitor array as with the case with output impedance control, a capacitance appears differently between the feedback capacitor and the gate electrode of a drive transistor due to bias voltage dependency, which makes control not easy.
Another method for solving the above problem is described in Japanese Patent Application Laid-Open No. 2000-59201. It describes a circuit configuration capable of keeping a constant rise and fall time of output data when the drive capacity of an output driver is changed. The semiconductor device is provided with an output terminal outputting data to the outside world, and a plurality of output circuits outputting signals to the output terminal. There are also provided a load adjustment circuit having a capacitance equal to an output circuit capacitance, and an output current adjustment switch circuit selecting between the output circuits and the load adjustment circuit. A drive line driven by a drive line driver is also provided to drive the output circuits using the output current adjustment switch circuit. In this configuration, an output current value is controlled, and the capacitance control allows the control of a rise and fall time of output data.
However, the conventional CMOS push/pull circuit and the circuit described in Japanese Patent Application Laid-Open No. 2000-59201 are difficult to design to attain stable signal transmission in high-speed data transmission such as newly offered by the USB 2.0 standard. At the same time, impedance matching or output level control is highly required for high-speed data transmission. Besides, as explained in the foregoing, the USB 2.0 standard further has the high-speed data transmission mode while retaining the conventional transmission modes. Therefore, the output buffer circuit is required to deal with a plurality of modes supporting widely different transmission speeds. The above conventional output buffer circuit, however, cannot meet the requirement.